1. Field of the Invention
The present invention relates to a package for housing an electronic device and, more particularly, to an improved package body and semiconductor chip package that does not use a substrate or metallic wires.
2. Background of the Related Art
A ball grid array (hereinafter, "BGA") semiconductor chip package employs a plurality of solder balls as external terminals. Such a BGA package is widely employed because it allows a multi-pin structure over a limited area. The external terminals in the related BGA package are sufficiently short to prevent bending by an external impact, while facilitating the transmission of electrical signals. In addition, the package is momentarily reflowed in a furnace when it is mounted on a motherboard, thereby shortening the mounting time.
As shown in FIG. 1, the related BGA package includes: a substrate 1; a semiconductor chip 3 fixedly mounted by an adhesive 2 on a central surface of the substrate 1; a plurality of chip pads 3a formed on an upper surface of the chip 3; a plurality of metallic wires 4 respectively connecting corresponding ones of the chip pads 3a to a metallic pattern (not shown) in the substrate 1; a molding compound 5 formed on the substrate 1 so as to cover the chip 3 and the metallic wires 4; and a plurality of solder balls 6 attached to a lower surface of the substrate 1.
The fabrication method of the related BGA package includes the steps of: a die bonding step for fixedly attaching the semiconductor chip 3 to the upper surface of the substrate 1; a wire bonding step for connecting metallic patterns (not shown) formed on the substrate 1 to corresponding chip pads 3a formed on the upper surface of the chip 3 with corresponding metallic wires 4; a molding step for forming the molding compound 5 to surround the chip 3 and the metallic wires 4 using an epoxy resin; and a solder ball attaching step for attaching the plurality of solder balls 6 on the lower surface of the substrate 1.
The size of the related BGA package is limited by the fact that the metallic wires 4 should have a constant loop height. Further, it is difficult and time consuming to carry out the wire bonding step for connecting the chip pads 3a to the metallic pattern (not shown) on the substrate 1 using respective metallic wires 4. This reduces the efficiency of the fabrication process.